Historical view of things like Line Code Violations, Path Code Violations, etc....
T1 0/0/0 is up.
Applique type is Channelized T1
Cablelength is long 0db
No alarms detected.
alarm-trigger is not set
Soaking time: 3, Clearance time: 10
AIS State:Clear LOS State:Clear LOF State:Clear
Version info FPGA Rev: 08121917, FPGA Type: PRK1
Framing is ESF, FDL is ansi & att, Line Code is B8ZS, Clock Source is Line Independent.
CRC Threshold is 320. Reported from firmware is 320.
Data in current interval (861 seconds elapsed):
0 Line Code Violations, 0 Path Code Violations
0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
Total Data (last 24 hours)
0 Line Code Violations, 255 Path Code Violations,
0 Slip Secs, 7 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,
29 Errored Secs, 17 Bursty Err Secs, 7 Severely Err Secs, 0 Unavail Secs
